Digital amplifiers are typically employed for high efficiency applications such as audio amplification in portable devices such as personal stereos where battery life is a significant consideration. They are also used in high power amplification where the high efficiency means that the size and cost of the power supplies and heatsinks can be reduced. These amplifiers typically utilise pulse width modulation (PWM) or pulse density modulation (PDM) to drive a switching power stage. However the source signals are typically stored as encoded sampled signals on a carrier such as a CD-ROM or as MP3 tracks on a memory device for example. Pulse Code Modulation (PCM) is a standard for encoding CD stored music samples, and hence a PCM-PWM Converter is needed to convert the multi-level PCM input signal to a two- or three-level PWM signal.
A schematic of a digital amplifier for digital audio and employing a PCM-PWM Converter is shown in FIG. 1, the amplifier comprising an over-sampling filter 1, a Converter 2, a power switch 3, a low pass filter 4, and a headphone or loudspeaker load 5.
The input to a digital Class-D amplifier is a series of (eg PCM) digital words representing signal amplitude levels over time. The over-sampling or interpolation filter adds additional samples from the incoming audio source samples by interpolating between the actual samples, thereby effectively increasing the sampling rate as is known. The over-sampled audio signal is fed to the Converter 2 which comprises a modulator to convert these words into a series of bits, (PDM) or on/off pulses of varying width (PWM) suitable for switching the switching element 3. The input signal modulates the output pulse width in the case of a Pulse Width Modulator, or the output pulse (bit) density in the case of a sigma-delta modulator. The power switch 3 switches a much larger output voltage into a low pass filter 4 which turns this signal into an analog signal for applying to the headphone or speaker load 5. The switch element 3 is either fully on or off and is switched at a high frequency with a duty cycle that is proportional to the amplitude of the input signal.
Referring to FIG. 2, a PCM-PWM Converter is shown which receives a series of digital words (PCM) representing signal amplitude samples over time. The PCM-PWM Converter 2 utilizes a linearizer 6, a word length reduction circuit (WLR) 7 and a PWM modulator 8.
The Pulse Width Modulator 8 generates an output which is either fully on or off (in a bi-phase or two-level application) and which is switched at a high frequency with a pulse width that is proportional to the amplitude of its input signal. The modulator 8 uses a saw-tooth modulation waveform which is compared with the incoming signal to determine the width of an output pulse as shown by the uniformly sampled PWM waveform in FIG. 3. In particular, a sample of the input signal is compared against the saw-tooth waveform, the vertical portion of which defines the start of a pulse corresponding to that sample. The end of the pulse for that sample occurs when the sloping part of the waveform crosses or equals the value of the sample. It can be seen that where the input signal amplitude is high, this will not occur until nearly the full duration of the pulse; and so a wide pulse will be output. Conversely where the signal input is low, the saw-tooth waveform will cross the input sample value early resulting in a narrow pulse width. This is known as Uniformly Sampled Pulse-Width Modulation. The sawtooth is generated using a digital counter circuit and therefore contains discrete steps.
A problem with PWM conversion of digitally sampled signals however, is that an error arises because the digital sample is held until it crosses the sawtooth waveform, whereas the equivalent analog signal is still varying. Therefore a width-error occurs in uniformly-sampled PWM. This can be seen in FIG. 3, which also shows Naturally Sampled Pulse-Width Modulation in which the corresponding analog input waveform is compared with the sawtooth waveform. This is theoretically free from harmonic distortion. In uniformly sampled PWM, the input waveform has already been regularly sampled at the points shown, and since the amplitude of the samples is different than in naturally sampled PWM at the point where the held sample crosses the sawtooth waveform, the width of the pulses are also different as shown.
Therefore the sampling process introduces some sampling error, resulting in harmonic distortion and noise-intermodulation. Noise-intermodulation is a process where high frequency noise components modulate with each other, or with high-frequency periodic components to produce noise products that fold back into the baseband. This reduces the baseband SNR of the system.
To reduce harmonic distortion and noise-intermodulation, a Lineariser 6 is often used to pre-distort the input signal to effectively cancel out the distortion introduced by the sampled nature of the input source. A Lineariser modifies the amplitude of the samples being fed into the modulator 8 so as to minimise the error between the pulse-widths that the modulator produces and the widths that would be produced from an equivalent analogue-input (naturally sampled) modulator, and hence to minimise the crossing point error outlined above. This is typically done by determining adjacent input sample values to derive a slope of the input signal, and adjusting one or both of these values in order to get a more accurate representation of the analogue signal at the cross point, and hence the end point of the corresponding pulse. This brings operation of the Converter 2 closer to the ideal natural sampled PWM resulting in lower levels of harmonic distortion and noise-intermodulation.
A common class of linearisation algorithm emulates Naturally Sampled PWM. The first published technique which emulates Naturally Sampled PWM is termed Enhanced Sampling and was introduced in P. H Mellor, S. P. Leigh and B. M. G Cheetham, “Reduction of spectral distortion in class D amplifiers by an enhanced pulse width modulation sampling process”, IEE Proceedings G, Circuits, Devices and Systems, vol 138 no 4, pp 441–448, August 1991. The algorithm estimates the time that the input signal crosses the reference waveform using a straight-line interpolation between adjacent samples. This cross-time is then used to calculate the width of each pulse, as shown in FIG. 4. It can be seen that the pulse-widths are a closer approximation of Naturally-Sampled PWM.
The problem with Enhanced Sampling is that the straight-line interpolation is not very accurate in determining the exact cross-time. The basic algorithm has therefore been enhanced in a number of ways, for example using polynomial interpolation as discussed in M. Sandler, J. Goldberg, R. Hiorns, R. Bowman, W. Watson, P. Ziman, “Ultra Low Distortion Digital Power Amplification”, AES 91st Convention, October 1991, preprint 3115 and C. Pascual, B. Roeckner, “Computationally Efficient Conversion from Pulse-Code Modulation to Naturally Sampled Pulse-Width Modulation”, AES 109th Convention, 2000 September.
In M. S. Pedersen, M. Shajaan, “All Digital Power Amplifier Based on Pulse-Width Modulation”, AES 96th Convention, February 1994. Preprint 3809, the sample-rate is increased using Interpolation filters to derive a center-point. Straight-line interpolation is then used between the center-point and the original points to derive a more accurate cross point. The sampling process can thereby be made to closely match the original naturally sampled waveform, hence the harmonic distortion is much reduced.
A problem with digital Pulse-Width modulators however is that they require the use of a high-frequency clock to precisely time the pulse-edges. The frequency of the clock depends on the wordlength of the PWM input. For an input of N-bits and oversampling rate Fs, the clock frequency required is Fs.2N, since each input amplitude is represented by a different pulse width. In a standard CD music application this implies a sampling rate of 352.8 kHz×216=23 GHz. Such a high clock rate is not practicable.
To reduce the input wordlength and hence reduce the clock frequency, a noise-shaper or a sigma-delta modulator (SDM) architecture is commonly employed before the PWM modulator 8, as the Word Length Reduction Circuit (WLR) 7. Both techniques use feedback within the WLR 7 to redistribute the quantization noise caused by reducing the wordlength to higher frequencies where it is less audible and can be filtered by the output filter 4 of the power switching stage.
To ensure that enough quantisation noise is scooped out of the baseband by this noise redistribution, a high order loop filter within the WLR is preferred, typically 4th or 5th order. For these high orders, the efficiency of implementation of the loop filter becomes important.
At high order it is common to use sigma-delta modulation, which commonly uses a cascade integrator structure for its loop filter that offers very low sensitivity to coefficient quantization. In practice it is possible to quantize the coefficients to only 1- or 2-bits without compromising the performance of the modulator. The multiplier can then be replaced by a small number of adds, reducing the complexity of the silicon design.
However, when a SDM WLR circuit 7 is used between the lineariser 6 and modulator 8, the linearisation algorithm fails, and distortion is present in the output signal. This is because the SDM (7) filters the incoming signal, effectively modifying the cross-points that have been calculated by the linearisation algorithm.
This problem has been addressed by combining the sigma-delta modulator and lineariser, such that the lineariser “sees” the output of the SDM directly and can therefore provide the necessary amplitude correction, as discussed in P. Craven. “Towards the 24-bit DAC. Novel Noise-Shaping Topologies Incorporating Correction for the Nonlinearity in a PWM Output Stage”, J. AES Vol 41, No 5 1993 May. However this solution is complex to implement.
Alternatively a Noise-shaper can be used, which does not filter the input signal, and so does not affect the performance of the linearizer. A commonly used class of high-order noise shaper WLR circuits are described in S. K. Tewkesbury, “Oversampled, Linear Predictive and Noise-Shaping Coders of Order N>1”, IEEE Trans. Circuits and Systems, vol CAS-25, pp 436–447, July 1978. This type of WLR circuit, while efficient to implement, has the disadvantage of having high gain at high frequencies, resulting in high levels of out-of-band noise. This increases the amount of noise-intermodulation introduced by the PWM modulator 8, producing a poor SNR at the output of the Converter 2.
More general IIR Filters can also be used as loop filters in a noise-shaping WLR circuit, for example Direct Form implementations, which can be designed with lower gain at high-frequencies. However these filters have high coefficient sensitivity, and therefore full multipliers with large coefficient word lengths are needed which are expensive to implement and requires extra silicon real-estate.